Saturday, December 18, 2010

Intel Westmere Clarkdale C-2 CM80616004641AB

Intel Westmere Clarkdale C-2 CM80616004641AB


Intel's latest 32nm desktop CPU (codename “Clarkdale) is the first member of Westmere processor family. Built on Intel’s second-generation high-k and metal gate transistor technology, the equivalent oxide thickness of the high-k dielectric has been reduced from 1.0nm on 45nm to 0.9nm on the 32nm process while gate length as been reduced to 30nm.

Intel Morrow Project



“The Morrow-Project” is a unique literary project which shows the important effects that contemporary research might have on our future and the relevance that this research has for each of us. Research currently being conducted by Intel in the fields of photonics, robotics, telematics, dynamic physical rendering and intelligent sensors served as the basis to inspire four bestselling authors. The results are four short stories which paint amusing, thought-provoking and hopeful pictures of our future.

Monday, December 13, 2010

The World’s First Computer Operating System Implemented at General Motors Research Labs in Warren, Michigan in 1955

Steve Holland from General Motors Research Laboratories said an interesting text about two of the three earliest operating systems: General Motors OS and GM-NAA I/O. I am publishing it here because when I tried to find some resources about this operating system, I realized that there are no a lot of sources on the Internet.

There is an interesting, but little known, relationship between the first FORTRANcompiler on the IBM 704 and the early development of operating systems. In 1955, what was probably the first operating system had been developed and was in use at theGeneral Motors Research Laboratories. Called the I/O system, it was a three-phase
system in that a batch of jobs was processed entirely with regard to input formats, then the entire batch was processed for execution, and finally the entire batch was processed for output conversion and printing. There were no higher-level languages in that system.

Shortly thereafter, IBM released the first version of the FORTRAN compiler as a set of programs on a magnetic tape, but without any listings of the source programs. The compiler itself consisted of a short bootstrap record on the tape, followed by many short records, each fully aware of the position of every other record on the tape, so that when a new procedure was to be brought in by loading another record from the tape, it was usually found by rewinding the tape and spacing out the appropriate number of records. Even this much organization had to be deduced without any documentation or listings.

Jim Fishman at General Motors did this analysis by obtaining an octal dump of the entire tape. He very carefully analyzed each instruction until he understood how the system worked. Without disturbing the order of the records, he then expanded some of them to include other components of what later became the excellent General Motors Research operating system. Thus the bootstrap loader grew from about 20 instructions to several thousand when it became the assembler preceded by the bootstrap loader in the same record. Later a relocatable loader was added, as well as other functions that we would now recognize as appropriate to an operating system. All this while FORTRAN never knew what happened!

A couple of years later, we adapted this operating system to our needs, beginning a long history of operating-system development at the University of Michigan.

Saturday, October 2, 2010



Sandy Bridge is Intel’s 2011 performance mainstream architecture refresh. It won’t take the place of the 6-core Gulftown based Core i7 processors at the top of the charts, but it’ll occupy the competitive space below it. The value segments won’t see Sandy Bridge until 2012.

The first CPUs will ship very early in 2011 for both desktops and notebooks. The architecture discussion we have here today applies to both. The CPUs won’t be called Sandy Bridge but instead will be called Intel’s 2nd generation Core i3/i5/i7 microrpocessors.

Sunday, April 25, 2010

HOWRAH BRIDGE- rabindra setu

The Howrah Bridge is a bridge that spans the Hooghly River in West Bengal, India. It was originally named the New Howrah Bridge because it links the city of Howrah to its twin city, Kolkata (Calcutta). On 14 June 1965 it was renamed Rabindra Setu, after Rabindranath Tagore a great poet and the first Indian Nobel laureate. However it is still popularly known as the Howrah Bridge.

The bridge is one of the four on the Hooghly River and is a famous symbol of Kolkata and West Bengal. The other bridges are theVidyasagar Setu (popularly called the Second Hooghly Bridge), the Vivekananda Setu and the newly built engineering marvelNivedita Setu. Apart from bearing the stormy weather of the Bay of Bengal region, it successfully bears the weight of a daily trafficof approximately 80,000 vehicles [1] and, possibly, more than 1,000,000 pedestrians. It is the sixth longest bridge of its type in the world.[2]

block diagram of L293D motor driver , AT89C52 and whole circuit



Saturday, April 24, 2010

ROBOTICS

COMPONENTS USED


 

  • Microcontroller(AT89C52)
  • Voltage Comparator(LM311P)
  • Motor Driver(L293D)
  • Variable Resistance
  • IR Sensor(GP2D12)
  • Crystal Oscillator(ML 11.0592)
  • Voltage Regulator(LM7805)

    
 


 


 


 


 


 


 

MICROCONTROLLER

(AT89C52 24PI)

The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8 Kbytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel's high density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pinout.


 

The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.


 



AT89C51 24PI


 

The AT89C52 provides the following standard features: 8 Kbytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16- bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.


 



 

                 Pin Configuration


 

Pin Description


 

VCC

Supply voltage.


 

GND

Ground.


 


 

Port 0


 

  • Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.


     

  • Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.


     


     

  • Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.


 


 


 

Port 1


 

  • Port 1 is an 8-bit bidirectional I/O port with internal pullups.


     

  • The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.


     


     

  • In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.


 


 


 



 

  • Port 1 also receives the low-order address bytes during Flash programming and program verification.


     


 

Port 2


 

  • Port 2 is an 8-bit bidirectional I/O port with internal pullups.


     

  • The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.


     

  • Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.


     

  • Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.


     


     

Port 3

  • Port 3 is an 8-bit bidirectional I/O port with internal pullups.


     

  • The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.


     

  • Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table.


     



 


 

  • Port 3 also receives some control signals for Flash programming

    and programming verification.


 


 

RST


 

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.


 


 


 


 

ALE/PROG


 

Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.


 

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcrontroller is in external execution mode.


 


 

PSEN


 

Program Store Enable is the read strobe to external program memory. When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.


 


 

EA/VPP


 

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming when 12-volt programming is selected.


 


 


 


 


 

XTAL1


 

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.


 


XTAL2


 

Output from the inverting oscillator amplifier.


 


 


 


 


 


 

BLOCK DIAGRAM OF AT89C52


 



Block Diagram of Microcontroller(AT89C52)


 

Interrupts


 

The AT89C52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure below. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table below shows that bit position IE.6 is unimplemented. In the AT89C51, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine

whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software.


 


 




 


 

Oscillator Characteristics


 

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure below. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure below. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.


 


 



 


Crystal Oscillator


 


 


ML 11.0592 crystal Oscillator


 


 


 


 


Maximum rating of AT89C51


 


 


 

VOLTAGE COMPARATOR

(LM311P)


 

The LM311 are single high-speed voltage comparators. These devices are designed to operate from a wide range of power-supply voltages, including 15-V supplies for operational amplifiers and 5-V supplies for logic systems. The output levels are compatible with most TTL and MOS circuits. These comparators are capable of driving lamps or relays and switching voltages up to 50 V at 50 mA. All inputs and outputs can be isolated from system ground. The outputs can drive loads referenced to ground, VCC+ or VCC–. Offset balancing and strobe capabilities are available, and the outputs can be wire-OR connected. If the strobe is low, the output is in the off state, regardless of the differential input.


 


 


 


 


 


                    LM 311 voltage comparator


 


 


 


                    Pin Configuration of LM311


 


 


 


 

Functional Block Diagram


 

                        


 


 

MOTOR DRIVER

(L293D)


 

The Device is a monolithic integrated high voltage, high current four channel driver designed to accept standard DTL or TTL logic levels and drive inductive loads (such as relays solenoides, DC and stepping motors) and switching power transistors. To simplify use as two bridges each pair of channels is equipped with an enable input. A separate supply input is provided for the logic, allowing operation at a lower voltage and internal clamp diodes are included.


 


 


 



 


 


 


 

BLOCK DIAGRAM


 


 



 

                    L293D Motor Driver


 

The L293D is a quadruple half H-bridge bidirectional motor driver IC that can drive current of up to 600mA with voltage range of 4.5 to 36 volts. It is suitable to drive small DC-Geared motors, bipolar stepper motor etc.

Specifications

  • Supply Voltage Range 4.5V to 36V
  • 600-mA Output current capability per driver
  • Separate Input-logic supply
  • It can drive small DC-geared motors, bipolar stepper motor.
  • Pulsed Current 1.2-A Per Driver
  • Thermal Shutdown
  • Internal ESD Protection
  • High-Noise-Immunity Inputs

Applications

  • DC and stepper motor drives
  • Position and velocity servomechanisms


 

PIN CONFIGURATION


 


Pin configuration of L293D

VARIABLE RESISTANCE

Variable resistors consist of a resistance track with connections at both ends and a wiper which moves along the track as you turn the spindle. The track may be made from carbon, cermet (ceramic and metal mixture) or a coil of wire (for low resistances). The track is usually rotary but straight track versions, usually called sliders, are also available.

Variable resistors are often called potentiometers in books and catalogues. They are specified by their maximum resistance, linear or logarithmic track, and their physical size. The standard spindle diameter is 6mm.



IR SENSORS

(GP2D12)

The GP2D12 sensor use triangulation and a small linear CCD array to compute the distance and/or presence of objects in the field of view.  The basic idea is this: a pulse of IR light is emitted by the emitter.  This light travels out in the field of view and either hits an object or just keeps on going.  In the case of no object, the light is never reflected and the reading shows no object.  If the light reflects off an object, it returns to the detector and creates a triangle between the point of reflection, the emitter, and the detector

        



The angles in this triangle vary based on the distance to the object.  The receiver portion of these new detectors is actually a precision lens that transmits the reflected light onto various portions of the enclosed linear CCD array based on the angle of the triangle described above.  The CCD array can then determine what angle the reflected light came back at and therefore, it can calculate the distance to the object. 


 


                 Sensing distance of GP2D12


 

CRYSTAL OSCILLATOR

(ML 11.0592)

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure below. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure below. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.


 


 

    


 



 


 

    


 

Why Two 33pF capacitors are used with crystal oscillator in 89c52 microcontroller?


 

Usually, crystal is between two pins of the CPU, and two caps of 33 pF are mounted from these pins to the ground.
The purpose is to "dephase" the crystal signal to provide a lead/lag to the buffers inside the CPU and allows the oscillation! (The oscillator is a feed-back loop around a buffer: you need input/output OUT OF PHASE to maintain oscillation. The caps shift the phase, while the Xtal maintains the frequency).


 

VOLTAGE REGULATOR

(LM7805)

The LM78M05 , a three-terminal positive voltage regulators employ built-in current limiting, thermal shutdown, and safe-operating area protection which makes them virtually immune to damage from output overloads.

With adequate heatsinking, they can deliver in excess of 0.5A output current. Typical applications would include local (on-card) regulators which can eliminate the noise and degraded performance associated with single-point regulation.

Features


 

Output current in excess of 0.5A

No external components

Internal thermal overload protection

Output voltages of 5V

  
  
  
 
  
  
  



 

OTHER COMPONENTS


 

RESISTORS

  • 10 kΩ
  • 8.2 kΩ
  • 330 kΩ


 

CAPACITORS

  • 10 µF
  • 330 µF
  • 0.1 µF
  • 33 pF


 

DIODES

1N4007

                                                                  


 


 


 

IC BASE

  • 40 pin
  • 16 pin


     



 


 


 


 


 


 


 

VERO BOARD    

Stripboard is a widely-used type of electronics
prototyping board characterized by a 0.1 inch (2.54 mm) regular (rectangular) grid of holes, with wide parallel strips of copper cladding running in one direction all the way across one side of the board. It is usually known by the name Veroboard, which is a trademark, in the UK, of British company Vero Technologies Ltd, who invented this kind of board.


 



 

WIRE CONNECTORS

These connectors are used to connect wires through the vero board through which input , power supply or outputs are taken out through the board.

Different conectors used are:

  • 8 pin
  • 4 pin
  • 2 pin


     


 


DC MOTOR (12V -50mA)



 


 


 


ROBOTIC WHEEL


 

Two types of wheel have been used:

  • Main wheel(Front)
  • Support wheel(Rear)


 


 


 


 



 


 


 

ROBOTIC BASE

It is made up of light weight material alumunium which provides easy movement of the robotic vehicle.It has folowing provision s in it:

  • Slot for DC motors.
  • Rear support wheel.
  • Slot to clamp sensors.
  • 9V battery holder.


 




 


 


 


 

Monday, February 1, 2010

Join the ASANSOL ENGINEERING COLLEGE group at www.linkedin.com

This group contain :
#Jobs in telecom, software, electronics ,IT, and electrical engineering.
#Discussions
#Books
#Presentations

Saturday, January 30, 2010

Introduction
What is a line follower?
Line follower is a machine that can follow a path. The path can be visible like a black
line on a white surface (or vice-versa) or it can be invisible like a magnetic field.
Why build a line follower?
Sensing a line and maneuvering the robot to stay on course, while constantly correcting
wrong moves using feedback mechanism forms a simple yet effective closed loop
system. As a programmer you get an opportunity to ‘teach’ the robot how to follow the
line thus giving it a human-like property of responding to stimuli.
Practical applications of a line follower : Automated cars running on roads with
embedded magnets; guidance system for industrial robots moving on shop floor etc.
Prerequisites:
Knowledge of basic digital and analog electronics.
(A course on Digital Design and Electronic Devices & Circuits would be helpful)
C Programming
Sheer interest, an innovative brain and perseverance!
Background:
I started with building a parallel port based robot which could be controlled
manually by a keyboard. On the robot side was an arrangement of relays connected to
parallel port pins via opto-couplers.
The next version was a true computer controlled line follower. It had sensors
connected to the status pins of the parallel port. A program running on the computer
polled the status register of the parallel port hundreds of times every second and sent
control signals accordingly through the data pins.
The drawbacks of using a personal computer were soon clear –
It’s difficult to control speed of motors
As cable length increases signal strength decreases and latency increases.
A long multi core cable for parallel data transfer is expensive.
The robot is not portable if you use a desktop PC.
The obvious next step was to build an onboard control circuit; the options – a
hardwired logic circuit or a uC. Since I had no knowledge of uC at that time, I
implemented a hardwired logic circuit using multiplexers. It basically mapped input from
four sensors to four outputs for the motor driver according to a truth table. Though it
worked fine, it could show no intelligence – like coming back on line after losing it, or
doing something special when say the line ended. To get around this problem and add
some cool features, using a microcontroller was the best option

Tuesday, December 1, 2009